1. Field of the Invention
The present invention relates to semiconductor testing apparatuses and methods of testing semiconductors for determining whether a semiconductor device under test is defective or not.
2. Description of the Related Art
A semiconductor testing apparatus provides a test signal as an output to a semiconductor device such as an integrated circuit, and determines whether the semiconductor device is defective or not based on a response signal supplied from the semiconductor device in response. The semiconductor testing apparatus includes plural semiconductor testing circuits, each of which is electrically connected to one of nodes of the semiconductor device under test (DUT). The semiconductor testing circuit applies a test signal to the node of the DUT, detects a response signal supplied from the DUT in response to the applied test signal, and compares the detected response signal with a predetermined reference signal. Generally, the semiconductor testing apparatus determines that the DUT is defective when the detected response signal does not match with the reference signal.
One type of such semiconductor testing circuits employs single transmission connection where an output part for the test signal and an input part for the response signal in the semiconductor testing apparatus are connected to the DUT via a single transmission line. When the single transmission connection is adopted, however, the semiconductor testing apparatus is held in a stand-by state during the reciprocation of the signal when the direction of signal transmission is changed. This delay is called a “round-trip delay.” Another type of the semiconductor testing circuits employs dual transmission connection where separate transmission lines are used for the connection between the DUT and the output part for the test signal in the semiconductor testing apparatus and for the connection between the DUT and the input part for the response signal in the semiconductor testing apparatus. When the dual transmission connection is employed, however, the amount of necessary wirings is doubled thereby complicates the structure of the semiconductor testing apparatus. In addition, the dual transmission connection cannot be utilized when driving capacity of the DUT is not sufficient, because the impedance of the line driven by an output terminal of the DUT is halved in the dual transmission connection.
Hence, a semiconductor testing circuit 601 as shown in FIG. 9 is proposed to eliminate such inconvenience (see U.S. Pat. No. 6,133,725). In the semiconductor testing circuit 601, a subtracter 616 receives at one input part thereof a composite signal generated as a sum of a test signal output from a driver 610 and a response signal output from a DUT 620. On the other hand, the subtracter 616 receives at another input part the test signal output from the driver 610. The subtracter 616 subtracts the test signal from the composite signal of the test signal and the response signal, to output the resulting signal to comparators 618 and 619 as a response signal. Each of the comparators 618 and 619 receives a predetermined reference signal to compare the same with the response signal. When the response signal does not match with the predetermined reference signal, each of the comparators 618 and 619 outputs a predetermined error signal. The semiconductor testing apparatus determines that the DUT 620 is defective when the comparators 618 and 619 output the error signals.
Thus, the semiconductor testing circuit 601 can eliminate the problem of the round-trip delay described above by supplying the response signal, which is a difference between the composite signal of the test signal and the response signal and the test signal, to the comparators 618 and 619. In addition, since the semiconductor testing circuit 601 is connected to the DUT 620 via a single transmission line 630, the apparatus can be realized in a simple structure. Further, another semiconductor testing circuit 701 as shown in FIG. 10 is proposed which includes a replica driver 720 in addition to the elements included in the semiconductor testing circuit 601 (see U.S. Pat. Nos. 6,563,298 and 6,703,825).
Here, the semiconductor testing circuits 601 and 701 respectively shown in FIGS. 9 and 10 are structured as to include the analog subtracter 616. Generally, it is difficult to satisfy requirements such as an improvement in operation precision, an increase in process speed, and adjustment to broad voltage range at the same time, with the analog subtracter. Hence, the semiconductor testing circuits 601 and 701 can adjust only to a limited voltage range and are incapable of performing a highly precise comparison at the comparators 618 and 619.
In addition, as shown in FIG. 11, an output stage 610b of the driver 610 has transistors 610c and 610d, which means presence of emitter resistance of the range from a few ohms (O) to a few ten O in the driver 610. Since the semiconductor testing circuits 601 and 701 are structured based on the assumption that the output impedance of the driver 610 is zero, a precise comparison as logically expected from the illustrations of FIGS. 9 and 10 cannot be realized in the semiconductor testing circuits 601 and 701 due to the presence of the emitter resistance in the driver 610. Thus, the precise determination on the defectiveness of the DUT is hampered.
Further, the semiconductor testing circuit 601 shown in FIG. 9 is structured as to require a point A, at which an output voltage of a signal output from the driver 610 is detected, between the driver 610 and an output resistor 612. On the other hand, an open collector type driver, for which a transistor serves as a coupling point, is structured as not to include the point A, at which the output voltage of a signal output from the driver 610 is detected. Hence, the open collector type driver cannot be utilized as the driver 610 in the semiconductor testing circuit 601. Thus, a driver structure employable in the semiconductor testing circuit 601 is limited.